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VSD - Physical Design Flow

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VSD - Physical Design Flow

VLSI - Building a chip is like building a city!!

4.5

(3299)

11614 enrolled on this course

Last updated 11/2021

Kunal Ghosh

₹ 2799.0

₹ 4299.0

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Lessons

Quizzes

Duration

13 Hours

Skill level

Beginner

Language

English

Certificate

Yes

Full lifetime access

Yes

Description

The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.

We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And also shared our industrial experience to give the technological exposure of current development in chip world...
Who this course is for:
Students looking for entry in VLSI World and explore new ways of solving problems

What you'll learn

Understand Industrial Physical Design Flow

Modify and Develop own Flow as per Specifications

Requirements

You will need a copy of Adobe XD 2019 or above. A free trial can be downloaded from Adobe.
No previous design experience is needed.
No previous Adobe XD skills are needed.

Course Content

27 sections • 95 lectures

Expand All Sections

1-Physical Design Flow Overview

1.1-Floor-Planning Steps

1.2-Netlist Binding And Placement Optimization

1.3-Placement Timing And Clock Tree Synthesis

1.4-Clock Net Shielding

1.5-Route - DRC Clean - Parasitics Extraction - Final STA

2-Floorplanning

2.1-Utilization Factor And Aspect Ratio

2.2-Concept Of Pre-Placed Cells

2.3-De-coupling Capacitors

2.4-Power Planning

2.5-Pin Placement And Logical Cell Placement Blockage

3-Placement

3.1-Net-list Binding And Placement

3.2-Optimize Placement Using Estimated Wire Length And Capacitance

3.3-Optimize Placement Conitnued

4-Timing Analysis With Ideal Clocks

4.1-Setup Timing Analysis And Introduction to Flip-Flop Setup Time

4.2-Introduction To Clock Jitter and Uncertainty

4.3-Setup Timing Analysis with Multiple Clocks

4.4-Multiple Clock Timing Analysis And Introduction To Data Slew Check

4.5-Data Slew Check

5-Clock Tree Synthesis And Signal Integrity

5.1-Clock Tree Routing And Buffering using H-Tree Algorithm

5.2-Crosstalk And Clock Net Shielding

5.3-Static Timing Analysis With Real Clocks

5.4-Hold Timing Analysis Concluded

5.5-Multiple Clocks Setup Timing Analysis With Real Clocks

6-Routing And Design Rule Check (DRC)

6.1-Introduction to Maze Routing - Lee's Algorithm

6.2-Lee's Algorithm Conclusion

6.3-Design Rule Check

7-Parasitics Extraction

7.1-Introduction to IEEE 1481 - 1999 SPEF format

7.2-SPEF Representation of a NET

7.3-Distributed Resistance And Capacitance Representation in SPEF

7.4-SPEF Header Description, Physical Design Flow Conclusion and What Next !!

8-Bonus - Technological advances happening in the world of opensource

8.1-Next Generation Education Technology for VLSI Design Flow

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